In conventional transistor structures, unsilicided source and drain extension regions may be formed between the transistor gate and silicided source and drain regions. These unsilicided source and drain extension regions have significant resistance which is in series with the transistor and significantly degrades the transistor performance.
In addition, in highly scaled semiconductor devices, the contact to gate space design rule is sufficiently small that the contact may land in part on the source/drain extensions. This is especially true when the contact is oversized or misaligned. Contact etch has much higher selectivity to silicide than it does to implanted silicon. In situations where the contact lands in part on the source/drain extensions, the contact etch step will etch part of the silicon and dopant from the exposed source/drain extensions. Loss of silicon and dopant from the source/drain extension causes higher series resistance degrading transistor performance. The contact etch may damage the silicon in the source/drain extension region which may give rise to increased junction leakage and higher standby current.
FIG. 1 shows a conventional transistor 1000 that has been processed through contact formation. The transistor includes a channel region 1002, a gate dielectric 1010, a polysilicon gate region 1020, offset spacer oxide 1012 and nitride 1014, sidewall spacer oxide 1016 and nitride 1018, source and drain extension regions 1004, source and drain diffusion regions 1006, source and drain silicide regions 1008, gate silicide region 1022, interlevel dielectric layer 1028, and contacts 1026. Contacts 1026 land in part on source/drain extensions 1004. As seen if FIG. 1, the etch process forming openings for contacts 1026 has etched away a significant portion of source and drain extensions 1004 so that contact portions 1030 extending from the bottom of contacts 1026 extend into source/drain extensions 1004.